The testing of memory circuits is important because even the slightest irregularities in raw materials and manufacturing processes may result in memory circuits which have one or more defective or failed memory elements. In order to provide a method of repairing such defective memories to improve yields, designers have developed memories which include redundant elements and circuitry for replacing the defective elements with redundant elements. Redundant elements typically include word line(s), bit line(s), or combinations of both, which are not initially assigned to any memory element(s) in the memory. While the testing of stand-alone memories in conventional Single-Inline Memory Modules (SIMMs) and Dual-Inline Memory Modules (DIMMs) is relatively straight forward, the testing of "embedded" memories poses special problems.
In particular, many circuits chips such as, for example, microprocessors, micro-controllers, and digital signal processors, have "embedded" memories. Embedded memories pose a special problem to testers because of their embedded design, i.e., they are surrounded by other circuits and logic. Accordingly, they are more difficult to test than their stand-alone counterparts because these circuit chips have fewer input and output pins available for the testing of their embedded memories. One attempt at overcoming this limitation is to include memory Array Built In Self-Test (hereinafter ABIST) circuitry within the chip. Generally, ABIST circuitry generates a plurality of test vectors which are applied (i.e., written) to the memory array. The ABIST then reads the output of the memory array and compares it with an expected result based on the applied test vectors to determine whether or not the test was successful.
To repair defective memory elements, single (i.e., word line or bit line) or two-dimensional (i.e., word line and bit line) redundancy calculations may be performed to determine where the redundant elements should be substituted. Two-dimensional redundancy calculations typically have the following general steps. Firstly, the redundant elements are tested to establish that they themselves are useable. Secondly, the memory array is tested and a "fail" image of the entire memory array is generated. The "fail" image identifies failed and good memory elements. Thirdly, post-processing of the "fail" image is performed to determine the best repair method for the image (i.e., where the redundant elements should be substituted). Once the best repair method is determined, the redundant elements are typically laser-fused into place.
The above-described general method of performing two-dimensional redundancy calculations is disadvantageous for several reasons. Firstly, it is very time-consuming because it requires separate testing of redundant elements and actual memory array elements. Secondly, the process is inefficient because it requires the generation and storage of large of amounts of test fail data so that a "fail" image of the entire memory can be generated. Thirdly, post-processing of the "fail" image to determine the best repair method for the memory is time-consuming and requires sophisticated external testing equipment. Accordingly, an apparatus and method which does not suffer from the above mentioned disadvantages is desirable. The second and third reasons are especially disadvantageous from an on-chip BIST viewpoint.